1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and an inspection method therefor. Specifically, the present invention relates to an inspection circuit for controlling fabrication steps of a semiconductor integrated circuit device, to a semiconductor integrated circuit device for evaluating and controlling fabrication processes and for analyzing a failure using the inspection circuit, and to an inspection method therefor.
2. Description of the Prior Art
In order to control the conditions of a fabrication line and to analyze causes of deterioration in characteristic of a semiconductor device in a fabrication process for fabricating a semiconductor integrated circuit on a semiconductor wafer, a test circuit including test elements is fabricated on the semiconductor wafer, the test circuit being used to easily and conveniently measure a characteristic of each element constituting a desired semiconductor integrated circuit. Each test element in the test circuit is measured during the fabrication process or at the end of the fabrication process to determine whether or not each test element complies with a predetermined function requirement, and the determined result is used to verify whether or not the fabrication process normally proceeds. If abnormality in characteristic is found in the test element, a more detailed evaluation is performed to identify causes of the abnormality.
In many cases, the test circuit is generally formed in a cutoff region of a semiconductor wafer. Along the cutoff region, semiconductor integrated circuits are cut from the wafer into semiconductor chips, and the cutoff region is referred to as a scribe line. Under such a condition that the scribe line is wide enough for a semiconductor wafer to be easily cut into semiconductor chips, it is desirable to minimize the line width of the scribe line in order to obtain as many semiconductor chips as possible from one semiconductor wafer. Therefore, a region provided for the test circuit is limited in area.
Meanwhile, along with the advancement of miniaturization and an increase in performance and an increase in integration in semiconductor process in recent years, requirements become more and more severe for variation in characteristics (electrical characteristics) of a semiconductor device formed on a semiconductor wafer, which makes it necessary to suppress the variation in characteristics as small as possible. In order to suppress the variation, it is necessary to measure a number of elements, for example, more than or equal to 1000 elements of the same type to check the standard deviation thereof. However, as described above, the number of measurements is limited in such a test circuit that is simply and conveniently structured to be formed in the scribe line region. Since number of pads which are connected to an external measurement apparatus used for measurement is also limited, it is difficult to measure a number of test circuits.
To cope with this problem, a measurement method is proposed in which test circuits using the limited number of pads are fabricated as many as possible in a limited area (see, for example, Japanese Laid-Open Patent Publication No. 2003-7785, which is hereinafter referred to as patent document).
A formation method of the test circuit disclosed in the patent document will be described below with reference to FIG. 17. As shown in FIG. 17, the test circuit includes: devices under test 102 arranged in rows and columns in a scribe region 100 of a semiconductor wafer; a column selection circuit 105 for selecting the devices under test 102 arranged in columns via column selection lines 103 and selection switches 104; a row selection circuit 107 for selecting the devices under test 102 arranged in rows via row selection lines 106 and the selection switches 104; common bus lines 110 connected to outside 101 of the semiconductor wafer via external measurement terminals 109 of the semiconductor wafer; and an address generation circuit 112 which is connected to an external control terminal 111 for receiving an external control signal and which generates an address for selecting one of the devices under test 102. Specifically, the address generation circuit 112 includes a shift register circuit and counts up an address signal by one address at a time up to the number of the devices under test 102 from the initial value according to a clock signal (not shown) from the outside. The common bus lines 110 are respectively connected to the row selection lines 106 via switch circuits 108. Each bus line 110 is connected to a measurement apparatus 113 in the outside 101 via each external measurement terminal 109.
Therefore, in the test circuit shown in FIG. 17, when an address control signal is input from the outside, the selected devices under test 102 are successively connected to the external measurement terminals 109. As a result, an electrical characteristic of each device under test 102 can be successively measured by the measurement apparatus 113. In this conventional example, the address generation circuit 112, the column selection circuit 105, and the row selection circuit 107 are provided to make it possible to successively measure a plural number of devices under test 102 with relatively few external control terminals 111 and signals.
However, an inspection method for the conventional semiconductor integrated circuit device adopts an electrical measurement in which a predetermined set-up voltage is applied to a device under test and a current flowing through the device under test is measured to evaluate a quality of the fabrication process.
In order to realize a high accuracy measurement, the measurement apparatus 113 performing the electrical measurement as illustrated with reference to FIG. 17 requires a waiting period, generally about several tens of milliseconds to several hundreds of milliseconds, per measurement of a device. The waiting period is a period after a predetermined applied voltage is set until the applied voltage stabilizes.
The test circuit disclosed in the patent document requires several tens of milliseconds to several hundreds of milliseconds after an address of a device under test 102 is advanced by one by the external control signal and the device under test 102 is measured until a measurement of a device under test 102 in a next address is initiated. Therefore, if the test circuit includes, for example, 1000 devices under test, measuring all of the devices under test 102 under only one condition takes several tens of seconds to several hundreds of seconds. If a whole area of the semiconductor wafer is measured while changing measurement conditions or the like for every device under test 102, there is a problem that an enormously long inspection time is required.
In a current fabrication process of semiconductor device, cost required for inspection constitutes a large proportion of the whole fabrication cost, and it is not cost-effective to spend such a long time for the inspection.